1. Field of the Invention
The present invention relates to a circuit for synthesizing a plurality of pulse signals whose phases are different from one another.
2. Description of the Prior Art
Conventionally, clock generation circuits have been known that generate a plurality of reference clock signals having phases shifted at even intervals by using a PLL (Phase Locked Loop) and then generate an output clock signal with a desired frequency by using the reference clock signals.
In Japanese Unexamined Patent Application Publication No. 5-83089 (Patent Document 1), a plurality of reference clock signals are generated, n AND circuits are each supplied with any two of the reference clock signals to generate n pulse signals (n is an integer equal to or greater than 2), and the n pulse signals are synthesized by a wired-OR circuit to generate a desired clock signal.
In Japanese Unexamined Patent Application Publication No. 2001-209454 (Patent Document 2), a plurality of reference clock signals are generated, n flip-flops are each supplied with any two of the reference clock signals to generate n pulse signals, and the n pulse signals are synthesized by a wired-OR circuit to generate a desired clock signal.
Thus, in the conventional techniques, n pulse signals are synthesized by a wired-OR circuit. The wired-OR circuit is generally formed by combining a plurality of logical elements. In an example of synthesizing five pulse signals, the wired-OR circuit has an OR circuit outputting the OR of two of the pulse signals, an OR circuit outputting the OR of three of the pulse signals, and an AND circuit outputting the AND of the outputs of the two OR circuits.
Also, FIG. 11 of Patent Document 2 illustrates an example of a wired-OR circuit. In the wired-OR circuit, the drain of each of n nMOS transistors and the drain of a pMOS transistor are connected to an input terminal of an inverter circuit. The source of the pMOS transistor is connected to a power supply node. The source of each of the nMOS transistors is connected to a ground node. Furthermore, n pulse signals are provided to the gates of the n nMOS transistors.